The present invention relates to a Digital-to-Analog converter circuit (hereinafter, simply referred to as D/A converter circuit) and a digital input class-D amplifier suitable for audio equipment, and the like.
As a technique for enhancing the accuracy of D/A conversion, there is a DEM (Dynamic Element Matching) technique. In a D/A converter circuit using the DEM technique, a plurality of lines of time-series digital signals having a density of “1” or “0” is generated by a decoder called a DEM decoder conforming to an input digital signal, and an analog signal which is a D/A conversion result is created by converting the plurality of lines of time-series digital signals into an analog signal respectively and adding them. Although the high linearity is obtained by the D/A converter circuit using the DEM decoder, the problem is that a limit cycle component appears in the analog signal which is the D/A conversion result, when the input digital signal has a somewhat different level from 0. For example, if the level of input digital signal goes slightly higher than 0 in plus direction, the “1” breaking the balanced state between the density of “1” and “0” appears in a plurality of lines of time-series digital signals outputted from the DEM decoder in low-frequency periodically, and it becomes a noise of low-frequency and appears in the analog signal which is the D/A conversion result. When the analog signal outputted from D/A converter circuit is used to drive a speaker, such a limit cycle component is not desirable because it becomes unpleasant noise to ears and is soundproofed from the speaker. Therefore, conventionally the measure which generates dither signals and adds them to the digital signal which is to be processed by the DEM decoder was being done. This measure can be divided into the method which adds DC dither as a dither signal to the digital signal which is to be processed by the DEM decoder (hereinafter, referred to as direct current dither method) and the method which adds alternating current signal of which the DC component is 0 (hereinafter, referred to as alternating current dither method). Also, such a type of the technique using a dither signal for a prevention of limit cycle is, for instance, disclosed on Patent Document 1, 2.
Patent Document 1: Japanese Patent Application Publication No. 2006-42272
Patent Document 2: Japanese Patent Application Publication No. 2006-304084
However, the above-mentioned direct current dither method has a disadvantage from the point that it needs a mean for preventing a DC offset from being supplied to the speaker which is a load, since the DC offset corresponding to the DC dither to be added to the digital signal which is to be processed by the DEM decoder appears in the analog signal which is the D/A conversion result. The alternating current dither method does not have such a disadvantage, because it uses the alternating current signal of which the DC component is 0 as the dither signal. However, in the case of using the alternating current dither method, the component of dither signal which is alternating current signal appears in the analog signal which is the D/A conversion result. Because the frequency of the component of the dither signal is low, there was a problem that it appears as a drive waveform of a load by passing an amplifier and the like, in the rear end of the D/A converter circuit.